Method and system for co-packaging vertical gallium nitride power devices

ABSTRACT

An electronic package includes a leadframe and a plurality of pins. The electronic package also includes a first gallium nitride (GaN) transistor comprising a source, gate, and drain and a second GaN transistor comprising a source, gate, and drain. The source of the first GaN transistor is electrically connected to the leadframe and the drain of the second GaN transistor is electrically connected to the leadframe. The electronic package further includes a first GaN diode comprising an anode and cathode and a second GaN diode comprising an anode and cathode. The anode of the first GaN diode is electrically connected to the leadframe and the cathode of the second GaN diode is electrically connected to the leadframe.

BACKGROUND OF THE INVENTION

Power electronics are widely used in a variety of applications. Power electronic devices are commonly used in circuits to modify the form of electrical energy, for example, from AC to DC, from one voltage level to another, or in some other way. Such devices can operate over a wide range of power levels, from milliwatts in mobile devices to hundreds of megawatts in a high voltage power transmission system. Despite the progress made in power electronics, there is a need in the art for improved electronics systems and methods of operating the same.

SUMMARY OF THE INVENTION

The present invention relates generally to electronic devices. More specifically, the present invention relates to co-packaging gallium nitride (GaN) electronics. Merely by way of example, the invention has been applied to methods and systems for manufacturing GaN power devices. The methods and techniques can be applied to a variety of semiconductor devices, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), bipolar transistors (BJTs, HBTs), diodes, and the like.

According to an embodiment of the present invention, an electronic package is provided. The electronic package includes a leadframe and a plurality of pins. The electronic package also includes a first gallium nitride (GaN) transistor comprising a source, gate, and drain and a second GaN transistor comprising a source, gate, and drain. The source of the first GaN transistor is electrically connected to the leadframe and the drain of the second GaN transistor is electrically connected to the leadframe. The electronic package further includes a first GaN diode comprising an anode and cathode and a second GaN diode comprising an anode and cathode. The anode of the first GaN diode is electrically connected to the leadframe and the cathode of the second GaN diode is electrically connected to the leadframe.

According to another embodiment of the present invention, a method of fabricating an electronic package is provided. The method includes providing a package comprising a leadframe and a plurality of pins and providing a set of gallium nitride (GaN) transistors, each comprising a drain contact, a source contact, and a gate contact. The method also includes joining the source contact of a first GaN transistor of the set of GaN transistors and the drain contact of a second GaN transistor of the set of GaN transistors to the leadframe and providing a set of GaN diodes, each comprising an anode contact and a cathode contact. The method further includes joining the anode contact of the first GaN diode and the cathode contact of the second GaN diode to the leadframe.

Numerous benefits are achieved by way of the present invention over conventional techniques. For example, embodiments of the present invention reduce the physical electronic package size of the power circuit when using GaN devices (e.g., a transistor, a diode, or the like) while still delivering high voltage and current ratings, which would, using conventional techniques, result in large, heavy packages. Capacitance may also be reduced as a result of smaller package sizes of GaN circuits, thereby reducing electromagnetic interference (EMI). Since GaN devices may be co-packaged closely together, parasitic inductance, resistance, and capacitance associated with interconnections between devices may be substantially reduced.

Additionally, GaN circuits are capable of operating at much higher frequencies than conventional silicon circuits without sacrificing power performance. Power electronics using conventional techniques may increase power loss and EMI when operated at higher frequencies. However, GaN power electronics reduce power loss and EMI, even at high frequencies.

Furthermore, co-packaged GaN power devices may provide more cost-effective solutions. For example, the GaN power electronics described herein co-package two GaN power devices (e.g., a transistor and a diode), such that only one electronic package and one heat sink is utilized. Co-packaging GaN devices also results in easier assembly of the electronic packages, less board space, and therefore less cost for the board and its enclosure. These and other embodiments of the present invention, along with many of its advantages and features, are described in more detail in conjunction with the text below and attached figures.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a top view of a GaN power device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view along the A-A′ direction illustrated in FIG. 1.

FIG. 3 is a cross-sectional view along the B-B′ direction illustrated in FIG. 1.

FIG. 4 is a cross-sectional view of a GaN diode according to an embodiment of the present invention.

FIG. 5A is a simplified schematic diagram of a half-bridge circuit 500 according to an embodiment of the present invention.

FIG. 5B is a simplified schematic diagram illustrating a semiconductor package including co-packaged vertical GaN power devices according to an embodiment of the present invention.

FIG. 6 is a simplified flowchart illustrating a method of fabricating a co-packaged GaN electronic device according to an embodiment of the present invention.

DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS

The present invention relates generally to electronic devices. More specifically, the present invention relates to co-packaging GaN electronics. Merely by way of example, the invention has been applied to methods and systems for manufacturing GaN power devices. The methods and techniques can be applied to a variety of vertical semiconductor devices, such as junction field-effect transistors (JFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), bipolar transistors (BJTs, HBTs), diodes, and the like.

GaN-based electronic devices are undergoing rapid development, and generally are expected to outperform competitors in silicon (Si) and silicon carbide (SiC). Desirable properties associated with GaN and related alloys and heterostructures include high bandgap energy for visible and ultraviolet light emission, favorable transport properties (e.g., high electron mobility and saturation velocity), a high breakdown field, and high thermal conductivity. In particular, electron mobility, μ, is higher than competing materials for a given background doping level, N. This provides low resistivity, ρ, because resistivity is inversely proportional to electron mobility, as provided by equation (1):

$\begin{matrix} {{\rho = \frac{1}{q\;\mu\; N}},} & (1) \end{matrix}$ where q is the elementary charge.

Another superior property provided by GaN materials, including homoepitaxial GaN layers on bulk GaN substrates, is high critical electric field for avalanche breakdown. A high critical electric field allows a larger voltage to be supported over smaller length, L, than a material with a lower critical electric field. A smaller length for current to flow together with low resistivity give rise to a lower resistance, R, than other materials, since resistance can be determined by equation (2):

$\begin{matrix} {{R = \frac{\rho\; L}{A}},} & (2) \end{matrix}$ where A is the cross-sectional area of the channel or current path.

The superior properties of GaN can give rise to improved semiconductor devices, especially power semiconductor devices. Prior art GaN power devices are typically lateral devices that utilize only the top side of a semiconductor wafer, locating electrical contacts such that electricity travels laterally along the semiconductor surface. This tends to consume a large surface area on the semiconductor. Vertical semiconductor devices, on the other hand, utilize a smaller surface area to achieve the same performance (i.e., forward current conduction capability) as lateral devices. Vertical semiconductor devices have electrical contacts on both the top surface of the semiconductor and on the bottom surface, or backside, such that electricity flows vertically between the electrical contacts. Vertical power devices are vertical semiconductor devices that can be utilized in high power and/or high voltage applications, such as power electronics.

A half-bridge circuit is the basic building block of most common power electronics topologies and may be used to effectively control the flow of electrical energy among a high-voltage supply, a low-voltage supply, and a load. Half-bridge circuits may typically include two transistors, acting as a switches, and two diodes. In a half-bridge circuit using traditional power semiconductor devices, such as silicon power devices, the transistors and diodes are typically devices that are packaged separately. The half-bridge circuit according to an embodiment of the present invention comprises GaN power transistors and GaN power diodes that both utilize a vertical architecture and are co-packaged together into a single electronic package. For a given voltage and current rating, GaN power devices may be significantly smaller than their silicon counterparts. For example, a 600V, 5 A GaN power device may have a surface area that is 100 times smaller than a 600V, 5 A silicon power device. Vertical GaN power devices may also be operated at much higher frequencies (e.g., 500 kHz-20 MHz) compared to vertical silicon power devices (e.g., up to 1 MHz) without a substantial increase in power loss. Embodiments of the present invention enable operation at high frequencies with greatly reduced noise, EMI, and power loss, by reducing or minimizing the parasitic inductance, resistance, and capacitance of the half-bridge circuit.

The GaN transistors and GaN diodes are co-packaged in an embodiment into a single electronic package to provide a total solution that is much smaller than what can be achieved by packaging the transistors and diodes separately, or co-packaging silicon transistors and silicon diodes. The capacitance of a power semiconductor device generally scales with area, so GaN power devices generally have much lower capacitance than similarly rated silicon power devices. Package-related capacitance also scales with size, so the electronic package-related capacitance is also greatly reduced as a result of smaller package sizes associated with GaN circuits. These lower capacitances provide greatly reduced switching losses for GaN power devices in comparison to similarly rated silicon power devices. Due to their small size, GaN devices may be co-packaged closely together, and parasitic inductance, resistance, and capacitance associated with interconnections between devices may be substantially reduced as the interconnection (e.g., current path) between these devices is made through a highly-conductive leadframe. Reducing these parasitic inductances greatly reduces electromagnetic interference (EMI), especially at high switching frequencies, and also reduces the over-voltage stress on the power semiconductor devices and other power electronic circuit elements. As a result, power electronics according to embodiments of the invention provide benefits and advantages such as faster switching, lower power loss, and less EMI than achieved with conventional approaches.

FIG. 1 illustrates a top-view of a GaN power transistor 100 including guard rings according to an embodiment of the present invention. Processes for the fabrication of vertical power transistor 100 are described in commonly assigned U.S. Patent Application Publication No. 2013/0032811, published on Feb. 7, 2013, entitled “METHOD AND SYSTEM FOR A GAN VERTICAL JFET UTILIZING A REGROWN GATE, U.S. Patent Application Publication No. 2013/0032812, published on Feb. 7, 2013, entitled “METHOD AND SYSTEM FOR A GAN VERTICAL JFET UTILIZING A REGROWN CHANNEL, U.S. patent application Ser. No. 13/675,826, filed on Nov. 13, 2012, entitled “LATERAL GAN JFET WITH VERTICAL DRIFT REGION, and U.S. patent application Ser. No. 13/735,897, filed on Jan. 7, 2013, entitled “GALLIUM NITRIDE VERTICAL JFET WITH HEXAGONAL CELL STRUCTURE,” the disclosures of which are hereby incorporated by reference.

GaN power transistor 100 includes a first gallium nitride layer 102 that is coupled to a substrate (not shown). In some embodiments, the substrate is a gallium nitride substrate. In some embodiments, first gallium nitride layer 102 can include an epitaxially grown gallium nitride layer, e.g., GaN that has n-type conductivity. First gallium nitride layer 102 can serve as a drift region and therefore can be a relatively low-doped material. For example, first gallium nitride layer 102 can have an n-conductivity type, with dopant concentrations ranging from 1×10¹⁴ cm⁻³ to 1×10¹⁸ cm⁻³. Furthermore, the dopant concentration can be uniform, or can vary, for example, as a function of the thickness of the drift region. In some embodiments, n-type dopants can include silicon, oxygen, selenium, tellurium, or the like.

The thickness of first gallium nitride layer 102 can also vary substantially, depending on the desired functionality. As discussed above, homoepitaxial growth can enable first gallium nitride layer 102 to be grown far thicker than heteroepitaxial GaN layers formed on non-GaN substrates. Thicknesses can vary between 0.5 μm and 100 μm, for example. In some embodiments thicknesses are greater than 5 μm. Resulting parallel plane breakdown voltages for GaN power transistor 100 can vary depending on the embodiment. Some embodiments provide for breakdown voltages of at least 100V, 300V, 600V, 1.2 kV, 1.7 kV, 3.3 kV, 5.5 kV, 13 kV, or 20 kV.

A second gallium nitride layer 108 can be epitaxially grown over first gallium nitride layer 102. Second gallium nitride layer 108, from which edge termination structures 104 are eventually formed, can have a conductivity type different than first gallium nitride layer 102. For instance, if first gallium nitride layer 102 is formed from an n-type GaN material, second gallium nitride layer 108 may be formed from a p-type GaN material, and vice versa. In some embodiments, second gallium nitride layer 108 is used to form the edge termination structures and is a continuous regrowth over portions of first gallium nitride layer 102 with other portions of the structure, such as regions of other semiconductor devices, characterized by reduced or no growth as a result of the presence of a regrowth mask (not shown). One of ordinary skill in the art would recognize many variations, modifications, and alternatives.

The thickness of second gallium nitride layer 108 can vary, depending on the process used to form the layer and the device design. In some embodiments, the thickness of second gallium nitride layer 108 is between 0.1 μm and 5 μm.

Second gallium nitride layer 108 can be highly doped, for example in a range from about 5×10¹⁷ cm⁻³ to about 1×10¹⁹ cm⁻³. Additionally, as with other epitaxial layers, the dopant concentration of second gallium nitride layer 108 can be uniform or non-uniform as a function of thickness. In some embodiments, the dopant concentration increases with thickness, such that the dopant concentration is relatively low near first gallium nitride layer 102 and increases as the distance from first gallium nitride layer 102 increases. Such embodiments provide higher dopant concentrations at the top of second gallium nitride layer 108 where metal contacts can be subsequently formed. Other embodiments utilize heavily doped contact layers (not shown) to form Ohmic contacts.

One method of forming second gallium nitride layer 108, and other layers described herein, can be through a regrowth process that uses an in-situ etch and diffusion preparation processes. These preparation processes are described more fully in U.S. patent application Ser. No. 13/198,666, filed on Aug. 4, 2011, entitled “Method and System for Formation of P-N Junctions in Gallium Nitride Based Electronics,” the disclosure of which is hereby incorporated by reference in its entirety. Second gallium nitride layer 108 can be used to form the gate region of vertical power transistor 100.

GaN power transistor 100 may also include an edge termination region. In the embodiment shown in FIG. 1, the edge termination region comprises one or more edge termination structures 104. In one embodiment, edge termination structures 104 are formed by removing at least a portion of second gallium nitride layer 108. The removal can be performed by a controlled etch using an etch mask (not shown but having the dimensions of the edge termination structures 104) designed to stop at approximately the interface between second gallium nitride layer 108 and first gallium nitride layer 102. Inductively-coupled plasma (ICP) etching and/or other common GaN etching processes can be used. In other embodiments, edge termination structures 104 may be formed by implanting ions into portions of second gallium nitride layer 108 to electrically isolate edge termination structures 104. In still other embodiments, the edge termination region may comprise a junction-termination extension (JTE) region, one or more field plates, deep trench termination, and/or a combination of these or other edge termination structures. Additional description related to edge termination regions is provided in U.S. patent application Ser. No. 13/334,742, filed on Dec. 22, 2011, entitled “METHOD AND SYSTEM FOR JUNCTION TERMINATION IN GAN MATERIALS USING CONDUCTIVITY MODULATION, the disclosure of which is hereby incorporated by reference in its entirety for all purposes.

As illustrated in FIG. 1, second gallium nitride layer/gate region 108 includes a continuous region 114 and one or more finger-like projections 118. Together, the continuous region 114 and projections 118 form the gate region of vertical power transistor 100. A gate electrode 112 is disposed over continuous region 114 and coupled to gate region 108 via gate contacts 120. In some embodiments, gate electrode 112 can include metals such as scandium, nickel, platinum, palladium, silver, gold, copper, aluminum, etc. and alloys thereof. In some embodiments, gate electrode 112 can be a multi-layered structure.

In one embodiment, at least some portions of the gate region may also include a low resistance layer (not shown) that may be disposed on top of the second gallium nitride layer. This low resistance layer may comprise a metal such as scandium, platinum, palladium, nickel, or other suitable materials. The purpose of this layer is to reduce the lateral resistance from gate electrode 112 to various locations on the gate region, which may be advantageous to reduce the distributed gate resistance of vertical power transistor 100 and, thus, improve the switching performance.

First gallium nitride layer 102 can be patterned and etched to form channel regions 106. Channel regions 106 are disposed such that there is one channel region in between two adjacent finger-like gate structures 118. These together form the p-n junction of a diode. Details of the placement of the source and gate structures are described more fully below. In one embodiment, a third gallium nitride layer (not shown) is coupled to first gallium nitride layer 102 and is etched to form channel regions 106. A source electrode 110 is coupled to channel regions 106 via source contacts 116. In some embodiments, source regions are interposed between channel regions 106 and source contacts 116, as described in reference to FIG. 3 below. In some embodiments, source electrode 110 can include metals such as scandium, titanium, aluminum, nickel, gold, copper, etc. and alloys thereof. In some embodiments, source electrode 110 can be a multi-layered structure.

As illustrated in FIG. 1, both source electrode 110 and gate electrode 112 are disposed within the edge termination region. This helps to isolate the low voltage gate and source electrodes from the high voltage of first gallium nitride layer 102. Connections to external systems can be made via electrodes 110 and 112 using wire bonding or other conventional techniques.

Although some embodiments are discussed in terms of a GaN substrate, embodiments of the present invention are not limited to GaN substrates. Other III-V materials, in particular, III-nitride materials, are included within the scope of the present invention and can be substituted not only for the illustrative GaN substrate, but also for other GaN-based layers and structures described herein. As examples, binary III-V (e.g., III-nitride) materials, ternary III-V (e.g., III-nitride) materials such as InGaN and AlGaN, and quaternary III-V (e.g., III-nitride) materials such as AlInGaN are also included within the scope of the present invention.

The GaN power transistor 100 utilizes an n-type drift layer that is grown on top of an n-type substrate. However, the present invention is not limited to this particular configuration. In other embodiments, substrates with p-type doping can be utilized. Additionally, embodiments can use materials having an opposite conductivity type to provide devices with different functionality. Thus, although some embodiments described herein include n-type GaN epitaxial layer(s) doped with silicon, other n-type dopants may be used, such as Ge, Se, S, O, Te, and the like. In other embodiments, highly or lightly doped material, p-type material, material doped with dopants such as Mg, Ca, Be, and the like can also be used. The substrates discussed herein can include a single material system or multiple material systems including composite structures of multiple layers. One of ordinary skill in the art would recognize many variations, modifications, and alternatives.

FIG. 2 illustrates a cross-sectional view of GaN power transistor 100 taken along the A-A′ line illustrated in FIG. 1. As described, current flow through the GaN power transistor occurs in a substantially vertical direction (referenced to the horizontal bottom surface of the substrate in the illustrations). Accordingly, embodiments of the present invention can be referred to as vertical GaN transistors or vertical power transistors. As illustrated in FIG. 2, vertical power transistor 100 includes a GaN substrate 202. A first GaN epitaxial layer 102 is coupled to and disposed over a surface of GaN substrate 202. A drain electrode 208 is coupled to an opposing surface of GaN substrate 202. In one embodiment, drain electrode 208 is formed from indium, titanium, aluminum, nickel, gold, or similar materials to provide an Ohmic contact. A second GaN epitaxial layer is disposed over and coupled to first GaN epitaxial layer 102. The second GaN epitaxial layer comprises continuous gate structure 114 and an edge termination region. As discussed above, the edge termination region may comprise multiple edge termination structures. The example of FIGS. 1 and 2 show three edge termination structures 104.

An interlayer dielectric layer (ILD) 210 is disposed over the gate structure 114 and edge termination structures 104. One or more gate contacts 120 are formed in ILD 210 to provide electrical connection between gate structure 114 and gate electrode 112. As can be seen, gate electrode 112 is located such that edge termination structures 104 completely surround gate electrode 112, thereby isolating gate electrode 112 from the high voltage present on the portion of first GaN epitaxial layer 102 that lies outside of the edge termination region.

FIG. 3 illustrates a cross section view of vertical power transistor 100 at the B-B′ line illustrated in FIG. 1. As illustrated in FIG. 3, channel regions 106 are disposed between adjacent finger-like projections 118 of gate region 108, creating p-n junctions. In one embodiment, a low resistance layer 306 is disposed on top of the at least some portions of gate region 108 and/or edge structures 104. Low resistance layer 306 may comprise a metal such as platinum, palladium, nickel, or other suitable materials. The purpose of low resistance layer 306 is to reduce the lateral resistance from gate electrode 112 to various locations on the gate region, which may be advantageous to reduce the distributed gate resistance of vertical power transistor 100 and, thus, improve the switching performance.

Source regions 304 are disposed on the top of channel regions 106. Source regions 304 may have the same conductivity type (e.g. N-type) as channel regions 106 and substrate 202. The doping concentration of source regions 304 may be substantially higher than the doping concentration of channel regions 106 in order to form a better Ohmic contact. Source electrode 110 is located such that edge termination structures 104 completely surround source electrode 110, thereby isolating source electrode 110 from the high voltage present on the portion of first GaN epitaxial layer 102 that lies outside of the edge termination region. Source region 304 is electrically coupled to source electrode 110 via source contacts 116. In one embodiment, source regions 304 are electrically isolated from gate region 108. For example, as shown in FIG. 3, the tops of finger-like projections 118 may be recessed below the tops of source regions 304 to provide electrical isolation.

In some embodiments, GaN substrate 202 can have an n+ conductivity type with dopant concentrations ranging from 1×10¹⁷ cm⁻³ to 1×10¹⁹ cm⁻³, and first GaN epitaxial layer 102 can have a n− conductivity type, with dopant concentrations ranging from 1×10¹⁴ cm⁻³ to 1×10¹⁸ cm⁻³. The thickness of first GaN epitaxial layer 102 can be anywhere from 0.5 μm and 100 μm or higher, depending on desired functionality and breakdown voltage. Channel region 106 can have a height of between 0.5 μm and 5 μm, a width of between 0.5 μm and 5 μm, and a n-type conductivity with a dopant concentration that is the same as or lower than the dopant concentration of first GaN epitaxial layer 102. In one embodiment, channel region 106 can be formed by etching away portions of first GaN epitaxial layer 102. Gate region 108 and the edge termination structures 104 can be from 0.1 μm and 5 μm thick and have a p+ conductivity type with dopant concentrations in a range from about 1×10¹⁷ cm⁻³ to about 1×10¹⁹ cm⁻³.

FIG. 4 illustrates a cross-sectional view of vertical GaN power diode 400 including GaN substrate 406 and first GaN epitaxial layer 404. Similar to the vertical GaN power transistor described above, GaN substrate 406 can have an n+ conductivity type with dopant concentrations ranging from 1×10¹⁷ cm⁻³ to 1×10¹⁹ cm⁻³, and first GaN epitaxial layer 404 can have a n− conductivity type, with dopant concentrations ranging from 1×10¹⁴ cm⁻³ to 1×10¹⁸ cm⁻³. The thickness of first GaN epitaxial layer 404 can be anywhere from 0.5 μm and 100 μm or higher, depending on desired functionality and breakdown voltage. GaN epitaxial regions 402 have a conductivity type opposite the conductivity type of first GaN epitaxial layer 404. For instance, first GaN epitaxial layer 404 is formed from an n-type GaN material and GaN epitaxial regions 402 are formed from a p-type GaN material. In some embodiments, the epitaxial regions 402 are formed using a continuous regrowth over portions of the first GaN epitaxial layer 404 with other portions of the structure, such as regions between the epitaxial regions 402, characterized by reduced or no growth as a result of the presence of a regrowth mask (not shown). One of ordinary skill in the art would recognize many variations, modifications, and alternatives.

The thickness of the epitaxial regions 402 can vary, depending on the process used to form the layer and the device design. In some embodiments, the thickness of the epitaxial regions 450 is between 0.1 μm and 5 μm. In other embodiments, the thickness of the epitaxial regions 450 is between 0.3 μm and 1 μm.

GaN epitaxial regions 402 can be highly doped with a P-type dopant such as magnesium, for example in a range from about 5×10¹⁷ cm⁻³ to about 1×10¹⁹ cm⁻³. The thickness of GaN epitaxial regions 402 can vary, for example, between 0.1 μm and 5 μm. The dopant concentration of GaN epitaxial regions 402 can be uniform or non-uniform as a function of thickness, depending on desired functionality. In some embodiments, for example, the dopant concentration increases with thickness, such that the dopant concentration is relatively low near first GaN epitaxial layer 404 and increases as the distance from the GaN substrate 406 increases. Such embodiments provide higher dopant concentrations at the top of the epitaxial regions 402 where a metal contact can be subsequently formed. Other embodiments utilize heavily doped contact layers (not shown) to form ohmic contacts.

One method of forming the epitaxial regions 402, and other layers described herein, can be through a regrowth process that uses an in-situ etch and diffusion preparation processes. These preparation processes are described more fully in U.S. patent application Ser. No. 13/198,666, filed on Aug. 4, 2011, the disclosure of which is hereby incorporated by reference in its entirety.

Top metal structure 410 forms an Ohmic electrical contact with at least some of GaN epitaxial regions 402. Top metal structure 410 is also in contact with portions of the first GaN epitaxial layer 404 that extend vertically between GaN epitaxial regions 402. Top metal structure 410 can be one or more layers of metal and/or alloys to create a Schottky barrier with the first GaN epitaxial layer 404. Thus top metal structure 410 forms the anode of a merged PN Schottky (MPS) diode. The cathode of the vertical GaN power diode is formed by bottom metal structure 408, which forms an Ohmic electrical contact with GaN substrate 406.

Some of GaN epitaxial regions 402 are used to provide an edge termination region of MPS diode 400. For example, ion implantation may be used to greatly reduce the conductivity of some areas of some of GaN epitaxial regions 402, as shown by first implanted regions 412, which leave thin conductive portions in some areas of GaN epitaxial regions 402, and by second implanted regions 414, which extend vertically through some areas of GaN epitaxial regions 402 to provide complete electrical isolation.

The MPS diode of FIG. 4 is shown merely by way of example. Many other embodiments of vertical GaN power diodes may be used to facilitate the present invention, including other configurations of MPS diodes, Schottky-barrier diodes, PN diodes, PiN diodes, and the like.

FIG. 5A is a simplified schematic diagram of a half-bridge circuit 500 according to an embodiment of the present invention. FIG. 5B is a simplified schematic diagram illustrating a semiconductor package including co-packaged vertical GaN power devices according to an embodiment of the present invention. Referring to FIG. 5A, the dashed line 505 represents a semiconductor package that houses four vertical GaN power devices: a high-side vertical JFET (J1), a low-side vertical JFET (J2), a high-side anti-parallel diode (Diode₁), and a low-side anti-parallel diode (Diode₂). The half-bridge circuit 500 and semiconductor package 505 include an output terminal 525, a high voltage terminal 510, a low voltage terminal 520, a control terminal 530 for the high-side JFET, a control terminal 540 for the low-side JFET, and optional source sense terminals for the high-side and low-side JFETs (535 and 545, respectively).

A primary function of the half-bridge circuit 500 is to connect the output terminal to either the HV terminal or the LV terminal by turning ON either the high-side JFET J1 or the low-side JFET J2. Thus, forward current can flow through J1 from HV 510 to OUT 525 or through J2 from OUT 525 to LV 520. Antiparallel diodes Diode₁ and Diode₂ are provided to conduct “reverse” current from LV 520 to OUT 525 and from OUT 525 to HV 510, respectively. In some embodiments, Diode₁ and Diode₂ may not be included, and the built-in body diodes of J1 and J2 may be used to conduct reverse current. However, the inclusion of Diode₁ and/or Diode₂ may help to alleviate some stress on the transistors J1 and J2, may help to spread the thermal dissipation and thus keep J1 and J2 cooler, and may provide better system efficiency. Voltages at the HV terminal can range from several volts (e.g., 5 V) to thousands of volts (e.g., 10,000 V), for example, 600 V, 1200 V, 1700 V, or the like. One of ordinary skill in the art would recognize many variations, modifications, and alternatives.

Referring to FIG. 5B, vertical GaN power transistors J1 and J2 and vertical GaN power diodes Diode₁ and Diode₂ are all mounted and co-packaged together in the same semiconductor package (also referred to as an electronic package), which may be much smaller than prior-art half-bridge circuits. GaN power devices are smaller in size than comparable silicon power devices or other semiconductor power devices (for example, 10× to 100× smaller). Because they are co-packaged together, the GaN transistors and GaN diodes can share a common leadframe 550A, which corresponds to the common output node 525 illustrated in FIG. 5A. The dotted line 506 in FIG. 5B illustrates an encapsulating material forming a body of the electronic package, with extensions (e.g., pins) 510A, 520A, 530A, 535A, 540A, and 545A corresponding to the terminals illustrated in FIG. 5A and protruding from the body of the electronic package to be electrically coupled to other connections.

The GaN transistors and GaN diodes are able to share the same leadframe 550A because transistor J2 (e.g., the vertical GaN power transistor discussed in relation to FIGS. 1-3) is mounted with its drain (D2 in FIG. 5A) electrically connected to the leadframe 550A of the electronic package, while transistor J1 (e.g., the vertical GaN power transistor discussed in relation to FIGS. 1-3) is mounted with its source (S1 in FIG. 5A) electrically connected to the leadframe 550A of the electronic package. Likewise, diode Diode₁ (e.g., the vertical GaN power diode discussed in relation to FIG. 4) is flipped over such that its anode terminal (A1 in FIG. 5A) is electrically connected to leadframe 550A, while diode Diode₂ is mounted with its cathode terminal (K2 in FIG. 5A) electrically connected to leadframe 550A.

Accordingly, as can be seen in the co-package illustrated in the half-bridge circuit 500, output node 525, which corresponds to leadframe 550A, is shared by four different device contacts. Thus, as illustrated in FIG. 5A, the electronic package features the source of transistor J1, the anode of diode Diode₁, the drain of transistor J2, and the cathode of diode Diode₂ all connected using a common electrode, which is the bond pad of the leadframe 550A illustrated in FIG. 5B.

Although the embodiment illustrated in FIG. 5B includes GaN transistors J1 and J2 and diodes Diode₁ and Diode₂ as discrete components, this is not required by the present invention. In other embodiments, the transistor(s) and diode(s) can be integrated as a monolithic device utilizing a single substrate. As an example, one or more GaN vertical transistors can be integrated with one or more diodes in a merged monolithic structure. Additional description related to monolithically integrated GaN transistors and diodes is provided in U.S. patent application Ser. No. 13/289,219, filed on Nov. 4, 2011, and entitled “Monolithically Integrated Vertical JFET and Schottky Diode,” the disclosure of which is hereby incorporated by reference in its entirety for all purposes. Thus, in an embodiment, transistor J1 and diode Diode₁ are monolithically integrated and transistor J2 and diode Diode₂ are monolithically integrated, facilitating higher performance, reliability, and the like. One of ordinary skill in the art would recognize many variations, modifications, and alternatives.

Half-bridge circuit 500 may provide for high currents, e.g., 5-10 A or more, to flow among the HV, OUT, and LV terminals. Therefore, in one embodiment of the invention, multiple pins and multiple bond wires may be used for the LV 520A and HV 510A connections, as shown in FIG. 5B. The common OUT 550A connection may conduct large currents directly through the leadframe 550A of semiconductor package 506.

In another embodiment, source sense terminals SS1 (535) and/or SS2 (545) may be made available in order to provide a signal reference for driving transistors J1 and/or J2, respectively. The addition of SS2 may be particularly advantageous in reducing the stray common mode inductance 538, in the electronic package and wire bonds, as well as external inductance on the circuit board to which package 505 is mounted, which can cause dynamic source degeneration. Rapid transition of current when the transistors J1 and J2 turn on or off can occur in a very short time duration owing to the small capacitance of GaN transistors. This dI/dt (i.e., change in current over time) of the source current can cause a voltage drop across the stray inductance (V=Lstray*dI/dt) and the resultant source degeneration has the effect of causing oscillation and limiting the dI/dt capability of the device. The source sense pins prevent the dI/dt from being fed back into the gate driver circuit.

The gate G1 of transistor J1 is electrically coupled to a top metal on transistor J1 and further electrically coupled to gate pin 530A. Referring to FIG. 2, the gate electrode 112 corresponds to either gate G1 of transistor J1 or gate G2 of transistor J2 in FIG. 5. Pin 530A of FIG. 5B may extend under the gate electrode of transistor J1 to facilitate electrical connection without need for a wire bond (e.g. using solder or conductive epoxy between pin 530A and G1). The source S1 of transistor J1 may be electrically coupled to leadframe 550A without need for a wire bond (e.g. using solder or conductive epoxy between leadframe 550A and S1). Source sense terminal SS1 of J1 may be formed by an extension of leadframe 550A (not shown), or may be electrically connected to leadframe 550A by a bond wire, as shown in FIG. 5B. The drain D1 of transistor J1 may be connected to HV pins 510A by bond wires, as shown.

The drain D2 of transistor J2 may be electrically coupled to leadframe 550A without need for a wire bond (e.g. using solder or conductive epoxy between leadframe 550A and D2). The source S2, source sense SS2, and gate G2 of transistor J2 may be electrically connected to LV pins 520A, SS2 pin 545A, and G2 pin 540A, respectively, by bond wires.

Vertical GaN power devices may have one or more top metal electrodes on a top surface, depending on the type of device. The embodiment in FIG. 4, for example includes a single electrode 410 on the top surface of the vertical GaN power MPS diode 400. On the other hand, as shown in FIGS. 1-3, other embodiments of vertical semiconductor devices, such as transistors, can include multiple top metal electrodes 110 and 112, i.e. the gate and source electrodes. The top metal electrodes may be formed from the same top metal layers which are patterned into different areas to form multiple electrodes, and these electrodes can be substantially co-planar or at multiple levels depending on the structure of the device layer(s).

Vertical GaN power devices may also include electrodes comprising metal layers coupled to the GaN substrate. Backside metals (also referred to herein as “back metals” or “backside metals”) are metals coupled to a bottom surface of a vertical GaN power device. These backside metals can be utilized in the packaging of GaN devices to provide mechanical, electrical, and thermal attachment between the GaN device and its housing or package. This low resistivity connection facilitating vertical current flow is particularly beneficial for vertical power devices. A backside metal can include one or more metal layers. Furthermore, in some embodiments, multiple metal contacts may be formed from a backside metal, depending on device functionality.

Often, the top metal and/or backside metal on semiconductor devices are not solderable. Accordingly, in many cases, devices are attached to a package leadframe with electrically insulating epoxy or electrically conductive (e.g., silver filled) epoxy, which is much less thermally conductive and has a much higher electrical resistivity than solder. Solder, on the other hand, has very good electrical and thermal conductivity. It is also known for good reliability under temperature cycling and environmental testing using high humidity levels at elevated temperatures. Therefore, for power semiconductor devices requiring good electrical and thermal connections, such as vertical power devices, the top metal and/or backside metal of the semiconductor device are preferably attached to the metal leadframe of an electronic package by soldering.

Techniques for providing a solderable back metal are also discussed in U.S. patent application Ser. No. 13/285,271, filed Jul. 19, 2012, entitled “GaN Power Device With Solderable Back Metal,” the disclosure of which is hereby incorporated by reference in its entirety for all purposes. These techniques are equally well suited to forming solderable top metal on vertical power devices that are meant to be mounted topside-down to the leadframe of an electronic package.

Other embodiments of this invention include vertical GaN power devices with top and/or backside metal that is suitable for other means for attaching the GaN power device to a package leadframe. For example, silver sintering is a method of attaching a semiconductor die to a package (i.e., a die-attach method) which may provide even better electrical and thermal conductivity than solder. A top metal and/or backside metal that includes an outermostlayer of gold, silver, or copper may be suitable for use with silver sintering. Another die-attach method that provides excellent electrical and thermal conductivity is eutectic die attach. A top metal and/or backside metal that includes an outermostlayer of gold may be suitable for use with eutectic die attach.

In the embodiment of FIGS. 5A and 5B, transistor J2 and diode Diode₂ may utilize a backside metal (i.e., drain electrode D2) that is compatible with soldering, sintering, or eutectic die attach, such that the backside of the transistor J2 die and the backside of the diode Diode₂ die can be mounted to leadframe 550 with good electrical and thermal conductivity. The top metal of transistor J1 and diode Diode₁ (i.e., anode A1) may comprise similar metal layers, such that the top of transistor J1 die and the top of diode Diode₁ die can be mounted to leadframe 550 with good electrical and thermal conductivity. Moreover, both transistor die and both diode die may share one or more die attach processes.

In some embodiments of the invention, the top metal and/or backside metal can include a metal stack with various layers to provide a bondable contact surface such that electrically-conducting structures (bonding wires, ribbons, copper clips, tabs, leads, and the like) may be coupled to the top

In some embodiments of this invention, the top metal and/or backside metal can comprise a diffusion barrier and/or pad metal. The diffusion barrier, coupled with a protection layer, can help prevent the protection layer from intermixing with other layers placed on top of the diffusion barrier. For example, for a protection layer comprising Au and a pad metal comprising Al, the diffusion barrier can help prevent the protection layer and pad metal from diffusing into each other and forming highly resistive intermetallics, like Au₅Al₂ and AuAl₂. Furthermore, depending on the composition of the protection layer and pad metal, the diffusion barrier can also act as an adhesion layer. Acceptable materials for the diffusion barrier can include Ni, Pt, Mo, W, TiW, titanium nitride (TiN) and/or Cr. In one embodiment, the diffusion barrier includes a bottom layer of Ti, which adheres well to both protection layer and dielectric layer, and an upper layer of Ni, Pt, W, TiW, or similar diffusion barrier layers. The thickness of the diffusion barrier can vary, depending on processing concerns (e.g., coverage), as well as other factors. In some embodiments, for example, the thickness of the diffusion barrier can be between 25 nm and 400 nm thick.

The pad metal provides a bondable surface to which wire (and/or other types) of bonds may be formed. Thick aluminum (Al) wires bonds are commonly used, for example, to form contacts in power electronics. Larger diameter (e.g. 50 μm-500 μm) Al wires provide a high current and low resistance path to the semiconductor device. In some embodiments, the pad metal can comprise Al, which is easily deposited, inexpensive, and readily bondable to Al bond wires. Additionally or alternatively, other materials, such as Cu, can be used. Furthermore, physical features and/or patterns of the pad metal and/or the diffusion barrier can be defined by material removal processes, such as a lithographical wet etch.

The thickness of the pad metal can vary, depending on composition, desired functionality, and/or other factors. The pad metal can be relatively thick to help ensure the structural integrity of the pad metal can withstand a subsequent wire bonding process. In particular, the Al wire bonding process exerts large forces on the pad metal. A thick pad metal can absorb these forces to prevent damage to the underlying GaN device layers. In some embodiments, for example, the thickness of the pad metal can be between 2 μm and 6 μm. In one embodiment, thickness is in the range of 3.5 μm to 4.5 μm. In the embodiment illustrated in FIGS. 5A and 5B, transistor J2 and diode Diode₂ may utilize a topside metal (i.e., gate electrode G2 540 and 540A and source electrode S2) that is compatible with wire bonding, ribbon bonding, copper clips, and/or other contact methods to make contact with pins 540A and 520A, respectively. The backside metal of transistor J1 and diode Diode₁ may comprise similar metal layers, such that when these devices are mounted topside down, the upward facing backside metal of J1 and Diode₁ die is compatible with the same topside contact methods to make contact with pin 510A. Moreover, the transistor die and diode die may share one or more die top-side contact processes. For example, copper clips may be attached to the upward facing surfaces of both die during the same processing step.

Techniques for providing a bondable contact metal may be used in conjunction with techniques for providing a solderable contact metal. These techniques for providing a solderable contact metal are also discussed in and U.S. patent application Ser. No. 13/611,467, filed Sep. 12, 2012, entitled “Bondable Top Metal Contact for Gallium Nitride Power Devices,” the disclosure of which is hereby incorporated by reference in its entirety for all purposes.

Referring to FIG. 5B, the drain D1 of transistor J1 is wire bonded to pins 510A along with the cathode K1 of diode Diode₁. The source S2 of transistor J2 is wire bonded to pins 520A along with the anode A2 of diode Diode₂. As described above, pins 535A and 545A are provided for connections to source sense terminal SS1 and source sense terminal SS2 as appropriate.

The exposed leadframe 550 of package 500 may be soldered to a heat sink (not shown) to facilitate heat removal from the power devices. Since the GaN transistors and GaN diodes are co-packaged and share the same leadframe, only one heat sink may be soldered to the electronic package, reducing the overall size, weight, and bulk of the electronic package. If the GaN transistor and GaN diode were to be packaged separately, each package would be typically be mounted to a heat sink, adding size and weight to the overall power converter. It should be noted that embodiments of the present invention provide electronic packages that are not suitable for packaging of conventional high power transistor and diode devices due to the comparatively large size of the conventional silicon-based (e.g., silicon carbide) devices since conventional devices cannot be packaged in the small packages discussed herein due to the heat generation and heat loading associated with conventional devices. Additionally, the vertical GaN transistors and vertical GaN diodes discussed herein enable high current densities in small packages (e.g., 5 mm×5 mm, 6 mm×6 mm, and 8 mm×8 mm packages) that are not achievable using conventional devices.

It should also be noted that the overmold packages described herein utilize mounting configurations not utilized in conventional designs. Referring to FIGS. 5A and 5B, GaN transistor J1 and GaN diode Diode₁ are mounted on the leadframe with substrate facing up. In conventional designs, since separate packages are utilized for each of the transistors and diodes, there is no benefit provided by mounting the transistors or diodes in the atypical substrate-up configuration. However, in the embodiments described herein, in order to provide the illustrated connections to the lead frame, flipping of the appropriate devices substrate-up prior to mounting provides benefits not achievable using conventional techniques.

Co-packaging the GaN transistors and the GaN diodes also reduces additional parasitic effects that result from separately packaging the devices and using interconnections between both packages. The longer and thinner the interconnections are between separate packages, the more inductance and resistance is introduced. Mounting the separate packages further apart on a circuit board magnifies the problems, resulting in ringing as these inductances are switching at high currents and high voltages and transitioning quickly, which also causes EMI problems. Increased EMI generates high frequency radiation which may negatively affect other devices mounted on the same circuit board as the GaN transistors and GaN diodes package.

Illustratively, the resulting package of co-packaging GaN transistors with GaN diodes may be much smaller than conventional silicon packages using conventional techniques. For example, two 600V/5 A GaN transistors and two 600V/5 A GaN diodes may be co-packaged in a 5 mm×5 mm package, while a conventional TO220 package for a 600V/5 A silicon transistor and a separate package for a 600V/5 A silicon diode measures approximately 10 mm×15 mm each. As such, the electronic package for a GaN electronic circuit may be 10 to 100 times smaller than a package for the corresponding silicon electronic circuit. In conventional TO220 packages, tabs may be at different voltages, therefore attached to separate heat sinks, which makes conventional TO220 packages of silicon devices and circuits even larger.

Furthermore, dual flat no-lead packages that can be utilized with the co-packaged GaN transistors and GaN diodes described herein may cost far less than traditional TO220 packages (e.g., 25-75% of the cost per package). The reduced size and bulk of co-packaged GaN devices results in reduced circuit board space, also lowering the cost assembly and manufacture of circuit boards and its enclosures. Additionally, since embodiments can utilize only one leadframe and one heat sink, materials and manufacturing costs are reduced further. For at least these reasons, methods and systems for manufacturing and fabricating GaN packages are more cost-effective and efficient than conventional methods and systems.

As illustrated in FIG. 5B, the electronic package includes a leadframe 550 and a plurality of pins. The two GaN transistors and two GaN diodes are mounted on the leadframe 550. Turning to each of the GaN transistors and GaN diodes, the GaN transistors include a drain region, a drift region, a source region, and a gate region. The drain region comprises a GaN substrate and a drain contact, the drift region comprises a first GaN epitaxial layer coupled to the GaN substrate, the source region is separated from the GaN substrate by the drift region and comprises a source contact, and the gate region comprises a second GaN epitaxial layer coupled to the first GaN epitaxial layer and a gate contact. The GaN diodes each include an anode region and a cathode region. The cathode region comprises the GaN substrate and a cathode contact and the anode region comprises a third GaN epitaxial layer coupled to the GaN substrate and an anode contact. The source contact of the first GaN transistor, the drain contact of the second GaN transistor, the anode contact of the first GaN diode, and the cathode contact of the second GaN diode are electrically connected to the leadframe.

FIG. 6 is a simplified flowchart illustrating a method of fabricating a GaN-based electronics package where a set of vertical GaN transistors are co-packaged with a set of GaN diodes according to an embodiment of the present invention. The method includes providing a package including a leadframe and a plurality of pins (602). Next, a set of GaN transistors is provided (604). In an embodiment, two GaN transistors are provided for co-packaging as described herein. Each of the GaN transistors may include a drain region, a drift region, a source region, and a gate region. In some embodiments, the drain region may comprise a GaN substrate and a drain contact. The source region may comprise a first GaN layer coupled to the GaN substrate and a source contact. The gate region may comprise a second GaN layer coupled to the GaN substrate and a gate contact. The method further includes joining the source contact of a first GaN transistor of the set of GaN transistors and the drain contact of a second GaN transistor of the set of GaN transistors to the leadframe (606).

In an embodiment, the GaN substrate is a n-type gallium nitride substrate, and the drift region may be a first GaN epitaxial layer coupled to a front surface of the GaN substrate. The first GaN epitaxial layer is characterized by a first dopant concentration, for example n-type doping with dopant concentrations ranging from 1×10¹⁴ cm⁻³ to 1×10¹⁸ cm⁻³. The thickness of the first GaN epitaxial layer may vary, depending on the process used to form the layer and the device design. For example, using homoepitaxy techniques, the thickness of the first GaN epitaxial layer may be between 1 μm and 100 μm. The gate region may be a second GaN epitaxial layer of an opposite type from the first GaN epitaxial layer coupled to the first GaN epitaxial later. The dopant concentration of the second GaN epitaxial layer may exceed the dopant concentrations of the first GaN epitaxial layer. For example, a p-type dopant concentration of the second GaN epitaxial layer can be equal to or greater than 1×10¹⁸ cm⁻³. The thickness of the second GaN epitaxial layer may vary, depending on the process used to form the layer and the device design. In some embodiments, the thickness of the second GaN epitaxial layer may be between 0.1 μm and 5 μm.

The method further includes providing a set of GaN diodes (e.g. two GaN diodes), each including an anode region and a cathode region (608). The cathode region may comprise the GaN substrate and a cathode contact. The anode region may comprise a GaN epitaxial layer coupled to the GaN substrate and an anode contact. The method includes joining the anode contact of the first GaN diode and the cathode contact of the second GaN diode to the leadframe (610), which is also joined with the source contact of the first GaN transistor and the drain contact of the second GaN transistor.

The GaN epitaxial layer of the GaN diodes may be coupled to the front surface of the GaN substrates, and may have similar properties to those of the first GaN epitaxial layers of the GaN transistors.

In an optional embodiment, the method further includes electrically connecting the cathode contact of the first GaN diode to a first pin in the plurality of pins of the leadframe and the anode contact of the second GaN diode to a second pin in the plurality of pins of the leadframe (612). In an embodiment of the invention, to accommodate high currents, the cathode contact of the first GaN diode and the anode contact of the second GaN diode may be electrically connected to one or more additional pins. The drain contact of the first GaN transistor and the source contact of the second GaN transistor are electrically connected to third and fourth pin in the plurality of pins, respectively (614), and the gate contacts are electrically connected to fifth and sixth pins in the plurality of pins, respectively (616)

It should be appreciated that the specific steps illustrated in FIG. 6 provide a particular method of fabricating a vertical power device according to an embodiment of the present invention. Other sequences of steps may also be performed according to alternative embodiments. For example, alternative embodiments of the present invention may perform the steps outlined above in a different order. Moreover, the individual steps illustrated in FIG. 6 may include multiple sub-steps that may be performed in various sequences as appropriate to the individual step. Furthermore, additional steps may be added or removed depending on the particular applications. One of ordinary skill in the art would recognize many variations, modifications, and alternatives.

It is also understood that the examples and embodiments described herein are for illustrative purposes only and that various modifications or changes in light thereof will be suggested to persons skilled in the art and are to be included within the spirit and purview of this application and scope of the appended claims. 

What is claimed is:
 1. An electronic package comprising: a leadframe; a plurality of pins; a first gallium nitride (GaN) transistor comprising a source, gate, and drain, wherein the source of the first GaN transistor has a surface in contact with the leadframe and is electrically connected to the leadframe; a second GaN transistor comprising a source, gate, and drain, wherein the drain of the second GaN transistor is electrically connected to the leadframe; a first GaN diode comprising an anode and cathode, wherein the anode of the first GaN diode is electrically connected to the leadframe; and a second GaN diode comprising an anode and cathode, wherein the cathode of the second GaN diode is electrically connected to the leadframe.
 2. The electronic package of claim 1 wherein: the drain of the first GaN transistor and the cathode of the first diode is electrically connected to a first pin of the plurality of pins; the gate of the first GaN transistor is electrically connected to a second pin of the plurality of pins; the source of the second GaN transistor and the anode of the second diode is electrically connected to a third pin of the plurality of pins; and the gate of the second GaN transistor is electrically connected to a fourth pin of the plurality of pins.
 3. The electronic package of claim 2 wherein the electrical connections of the drain of the first GaN transistor and the source and gate of the second GaN transistor comprise at least one of wire bonds, ribbon bonds, or copper clips.
 4. The electronic package of claim 1 wherein: the electrical connection between the anode of the first diode and the leadframe comprises at least one of epoxy, eutectic, sintering, or solder; and the electrical connection between the cathode of the second diode and the leadframe comprises at least one of epoxy, eutectic, sintering, or solder.
 5. The electronic package of claim 1 wherein: the electrical connection between the drain of the second GaN transistor and the leadframe comprises at least one of epoxy, eutectic, sintering, or solder; and the electrical connection between the source of the first GaN transistor and the leadframe comprises at least one of epoxy, eutectic, sintering, or solder.
 6. The electronic package of claim 2 wherein the second pin of the plurality of pins extends under a gate pad of the first GaN transistor and the electrical connection between the gate of the first GaN transistor and the second pin of the plurality of pins comprises at least one of epoxy, eutectic, sintering, or solder.
 7. The electronic package of claim 1 wherein the gallium nitride-based electronics package is electrically coupled and attached to a circuit board, wherein the leadframe is configured to conduct current from the source of the first GaN transistor, the drain of the second GaN transistor, the anode of the first GaN diode, and the cathode of the second GaN diode directly to the circuit board.
 8. The electronic package of claim 1 further comprising one or more heat sinks attached to the leadframe.
 9. The electronic package of claim 1 wherein the drain of the second GaN transistor and the source and the gate of the first GaN transistor comprises a solderable metal stack.
 10. The electronic package of claim 1 wherein the drain of the first GaN transistor and the gate and source of the second GaN transistor comprises a bondable metal stack.
 11. The electronic package of claim 1 wherein the source of the second GaN transistor is electrically connected to a fifth pin of the plurality of pins. 